Storage device controlling device and control method for storage device controlling device

ABSTRACT

A storage device controller has a channel controller, a disk controller, and a first memory for storing data delivered between the channel controller and the disk controller. The channel controller has a circuit board on which a first processor, a file access processor having a second processor and a second memory, a data transfer device and a third memory are formed. The second processor transmits information indicating the storage position of data in the second memory to the first processor, the first processor writes into the third memory data transfer information containing information indicating the storage position of data in the first memory and information indicating the storage position of the data in second memory, and the data transfer device reads out data transfer information from the third memory and controls the data transfer between the first memory and the second memory based on data transfer information thus read out.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application is a continuation of application Ser. No.10/771,465, filed Feb. 5, 2004, claims priority from Japanese PatentApplication No. 2003-368591, filed on Oct. 29, 2003, the entiredisclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a storage device controller, and amethod of controlling the storage device controller.

The amount of data to be handled in a computer system has recentlyincreased. In connection with this increase in the data amount, alarge-scale storage system equipped with a storage volume which ismanaged by a RAID (Redundant Arrays of Inexpensive Disks) system forsupplying enormous storage resources, referred to as a mid-range classor enterprise class, has recently received widespread attention as astorage system for managing large amounts of data. Furthermore, atechnique in which information processing devices are connected to astorage system through a dedicated network (Storage Area Network,hereinafter referred to as a “SAN”) to enable a large amount of accessto the storage system at high speed has been developed to efficientlyuse and manage vast amounts of data.

Furthermore, a storage system called a NAS (Network Attached Storage)has been developed for mutually connecting a storage system and aninformation processing device through a network using the TCP/IP(Transmission Control Protocol/Internet Protocol) protocol or the likeand for implementing access to data based on a file-name indication fromthe information processing device.

Such a storage system as described above uses a DMA (Direct MemoryAccess) transfer technique for eliminating transferring of data throughthe CPU (Central Processing Unit) in order to increase the data accessspeed. In order to carry out DMA transfer, the CPU writes into aregister equipped to a DMA controller, data transfer information neededfor data transfer, such as a transfer source storage address, a transferdestination storage address, etc. for data to be transferred, andinstructs the DMA controller to start the data transfer. Accordingly,the data transfer is carried out by the DMA controller without involvingthe CPU in the data transfer (see JP-A-2003-22246).

However, it takes more time to carry out data writing from the CPU intothe register of the DMA controller in the data transfer circuitcontaining the DMA controller as compared with data writing from the CPUinto a memory element. Therefore, in a situation in which data transferoccurs frequently, the time needed for the DMA starting processinginvolving the data writing from the CPU into the register of the DMAcontroller inhibits an increase in the data access speed.

Furthermore, in a situation in which data input/output control iscarried out by using plural CPUs, when data transfer is carried outbetween memories, each of which is controlled by a respective CPU, theCPU for controlling the DMA controller is required to obtain informationon storage addresses, etc. of data in the memories controlled by theother CPUs. Moreover, in a situation in which the data transfer size isdifferent for each memory, the CPU for controlling the DMA controller isrequired to provide control for adjusting the data transfer size. Anincrease in the processing load imposed on the CPU for controlling theDMA controller inhibits an increase of the data access speed. Therefore,it has been required to reduce the processing load imposed on the CPUfor controlling the DMA controller.

SUMMARY OF THE INVENTION

The present invention has been implemented in view of the foregoingproblem, and it has a main object to provide a storage device controllerand a method of controlling the storage controller.

In order to achieve the forgoing object, according to a first aspect ofthe present invention, there is provided a storage device controllercomprising a channel controller for receiving a data input/outputrequest based on a file-name indication received from an informationprocessing device through a network and for transmitting/receiving datato/from the information processing device, a disk controller forcarrying out input/output control of data stored in a storage volume forstoring the data, and a first memory for storing the data deliveredbetween the channel controller and the disk controller. The channelcontroller is equipped with a first processor for outputting ablock-basis I/O request corresponding to the data input/output requestand for controlling the first memory; a file access processor, which hasa second processor and a second memory controlled by the secondprocessor, and which serves to control the transmission/reception of thedata input/output request and the data which is carried out with theinformation processing device; a data transfer device for controllingdata transfer between the first memory and the second memory, and athird memory controlled by the first processor, which are formed on acircuit board. Wherein, the second processor transmits informationindicating the storage position of the data in the second memory to thefirst processor; the first processor writes into the third memory datatransfer information containing information indicating the storageposition of the data in the first memory and information indicating thestorage position of the data in the second memory; and the data transferdevice reads out the data transfer information from the third memory andcontrols the data transfer between the first memory and the secondmemory on the basis of the data transfer information thus read out.

Here, the storage device controller is defined as a device forcontrolling the reading/writing of data into the data-stored storagevolume in accordance with a data input/output request received from theinformation processing device. The information processing device isdefined as information equipment, such as a computer or the like, whichis equipped with a CPU and a memory. When the information processingdevice is connected to the storage system containing the storage devicecontroller and the storage volume or another information processingdevice through a network, such as a LAN (Local Area Network), SAN or thelike, it transmits/receives data to/from the storage system or the otherinformation device by communicating with the storage system or the otherinformation device. The storage volume is a storage resource for storingdata, and it contains the physical volume corresponding to a physicalstorage area supplied from a disk drive, such as a hard disk device orthe like, and the logical volume corresponding to a storage arealogically set on the physical volume.

The file access processor transmits/receives data based on a file-nameindication to/from the, information processing device. The functions ofthe file access processor are supplied from an operating system executedby the second processor and software, such as a NFS (Network FileSystem) or the like, which is operated on the operating system.

The first processor contains, as a hardware element, an IC (IntegratedCircuit) which is independent of the second processor serving as thehardware element of the file access processor, and it controls the firstmemory. The first processor outputs a block-basis I/O request inresponse to a file-basis data input/output request received from theinformation processing device by the file access processor. On the basisof the I/O request, the disk controller carries out the input/outputcontrol of data stored in the storage volume. The first memory comprisesa cache memory to be described later, for example. The data transferdevice functions as a DMA controller.

Accordingly, for example, when the file access processor receives a datawriting request and writing data based on the file name indication fromthe information processing device, the writing data is stored in thesecond memory. The first processor outputs the block-basis write requestcorresponding to the data writing request based on the file nameindication. The data transfer device transfers the writing data storedin the second memory to the first memory. On the basis of the writerequest, the disk controller reads out the writing data from the firstmemory, and also writes the writing data into the storage volume on ablock basis.

When the file access processor receives the data read-out request basedon the file name indication from the information processing device, thefirst processor outputs the block-basis read request corresponding tothe data read-out request based on the file name indication. The diskcontroller reads out data from the storage volume on a block basis onthe basis of the read request, and it also writes the read-out data intothe first memory. The data transfer device transfers the read-out datastored in the first memory to the second memory. The file accessprocessor transmits the read-out data stored in the second memory to theinformation processing device.

The input/output of the data stored in the storage volume is carried outthrough the communications between the disk controller and the storagevolume. The communications between the disk controller and the storagevolume may be carried out through a communication path constituting aloop which is set according to FC-AL of fibre channel standards.

When the data transfer device controls the data transfer between thefirst memory and the second memory, the data transfer device needs tostore the storage positions of data in the respective memories (thetransfer source address and the transfer destination address for thedata concerned) into a register. In the storage device controller ofthis invention, the data transfer information containing the informationindicating the storage positions of the data is written in the thirdmemory by the first processor. The data transfer device reads out thedata transfer information from the third memory and stores it into theregister. Therefore, the first processor writes the data transferinformation, not into the register of the data transfer device, whichrequires a relatively long access time, but into the third memory, whichrequires only a relatively short access time, and then shifts toexecution of the subsequent processing. Accordingly, the idle time ofthe first processor (standby time for writing completion) can bereduced, and the first processor can be efficiently operated. Therefore,the speed of the data reading/writing for the data input/output requestfrom the information processing device can be increased.

As described above, the data reading/writing speed can be increased. Theincrease in data reading/writing speed greatly contributes to anincrease in amount of data which is able to be handled in theinformation processing system and also to enhancement in the processingperformance of the overall information processing system under a usecondition of a recent storage system in which data input/output requestsare successively transmitted from many information processing deviceson-line and on a real-time basis.

The forgoing problems and the solutions thereof as provided by thisinvention will be more apparent from the following “Detailed Descriptionof the preferred Embodiments” and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the overall construction of a storagesystem according to an embodiment of the present invention;

FIG. 2 is a diagram showing the outside appearance of the storage systemaccording to the embodiment;

FIG. 3 is a diagrammatic perspective view showing the appearance of astorage device controller according to the embodiment;

FIG. 4 is a block diagram showing the construction of a managementterminal according to the embodiment;

FIG. 5 is a diagram showing a physical disk managing table according tothe embodiment;

FIG. 6 is a diagram showing an LU managing table according to theembodiment;

FIG. 7 is a block diagram showing a CHN according to the embodiment;

FIG. 8 is a block diagram showing a CHF, CHA according to theembodiment;

FIG. 9 is a diagram showing meta data, and a lock table according to theembodiment;

FIG. 10 is a block diagram showing a disk controller according to theembodiment;

FIG. 11 is a diagram showing the software construction of the storagesystem according to the embodiment;

FIG. 12 is a diagram showing a cluster construction of the storagesystem according to the embodiment;

FIG. 13 is a diagram showing the meta data according to the embodiment;

FIG. 14 is a diagram showing the lock table according to the embodiment;

FIG. 15 is a block diagram showing the construction of the DMA unitaccording to the embodiment;

FIG. 16 is a diagram showing a memory 2 according to the embodiment;

FIG. 17 is a diagram showing a memory 1 according to the embodiment;

FIG. 18 is a diagram showing a cache memory according to the embodiment;

FIG. 19 is a flowchart showing the flow of the DMA transfer processingaccording to the embodiment;

FIG. 20 is a flowchart showing the flow of the DMA transfer processingaccording to the embodiment;

FIG. 21 is a flowchart showing the flow of the script achievingprocessing according to the embodiment;

FIG. 22 is a flowchart showing the flow of the DMA transfer unitdetermining processing according to the embodiment;

FIG. 23 is a flowchart showing the flow of the transfer end judgementprocessing according to the embodiment;

FIG. 24 is a diagram showing a specific example of the DMA transferaccording to the embodiment;

FIG. 25 is a diagram showing a memory 2 according to the embodiment;

FIG. 26 is a diagram showing a memory 1 according to the embodiment;

FIG. 27 is a flowchart showing the flow of the DMA transfer according tothe embodiment; and

FIG. 28 is a block diagram showing the construction of an informationprocessing device according to the embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment according to the present invention will bedescribed hereunder with reference to the accompanying drawings.

First Embodiment

[Overall Construction]

First, the overall construction of a storage system 600 containing astorage device controller 100 according to an embodiment of the presentinvention will be described with reference to the block diagram of FIG.1.

The storage system 600 is equipped with a storage device controller 100and a disk drive device 300. The storage device controller 100 controlsthe disk drive device 300 according to a command received from aninformation processing device 200. For example, the storage system 600receives a data input/output request from the information processingdevice 200, and it reads/writes data stored in a storage volume 310equipped to the disk drive device 300. The storage volume 310 is definedas a storage resource for storing data, which contains a physical volumeserving as a physical storage area supplied by a disk drive, such as ahard disk device or the like, and a logical volume serving as a storagearea set logically on the physical volume. The storage volume 310 or thelogical volume will also hereinafter be referred to as a “LU (LogicalUnit)”. The storage device controlling device transmits/receives variouscommands for managing the storage system 600 to/from the informationprocessing device 200.

The information processing device 200 constitutes information equipment,such as a computer or the like, which is equipped with CPU and a memory.Various kinds of programs are executed by the CPU equipped in theinformation processing device 200 to thereby implement variousfunctions. The information processing device 200 may be a personalcomputer or a work station, or a main frame computer.

In FIG. 1, information processing devices 1 to 3 (200) are connected tothe storage device controller 100 through a LAN (Local Area Network)400. The LAN 400 may be the Internet or a dedicated network. Thecommunications carried out between the information processing devices 1to 3 (200) and the storage device controlling device 100 through the LAN400 are carried out according to the TCP/IP protocol, for example. Adata access request based on a file name indication (data input/outputrequest on the basis of a file-name indication, hereinafter referred toas a “file access request”) is transmitted from the informationprocessing devices 1 to 3 (200) to the storage system 600.

A backup device 910 is connected to LAN 400. Specifically, the backupdevice 910 may be a disc type device, such as a MO (Magneto-opticalDisc), CD-R (Compact Disc-Recordable), DVD-RAM (digital VideoDisc-Random Access Memory) or the like, or it may be a tape type device,such as a DAT (Digital Audio Tape) tape, a cassette tape, an open tape,a cartridge tape or the like. The backup device 910 communicates withthe storage device controller 100 through the LAN 400 to store backupdata consisting of data stored in the disk driving device 300.Furthermore, the backup device 910 may be connected to the informationprocessing device 1 (200). In this case, it can achieve the backup ofdata stored in the disk driving device 300 through the informationprocessing device 1 (200).

The storage device controller 100 is equipped with channel controllers 1to 4 (110). The storage device controller 100 communicates with theinformation processing devices 1 to 3 (200) and the backup device 910through the LAN 400 under control of the channel controllers 1 to 4(110). Each of the channel controllers 1 to 4 (110) receives a fileaccess request transmitted from each of the information processingdevices 1 to 3 (200) through LAN 400 and transmits/receives data to/fromthe information processing device. That is, a network address (forexample, IP address) on the LAN 400 is allocated to each of the channelcontrollers 1 to 4 (110). Therefore, each channel controllerindividually behaves as a NAS, and, thus, each of the channelcontrollers 1 to 4 can provide the information processing devices 1 to 3(200) with services of a NAS as if independent NASs exist. The channelcontrollers 1 to 4 (110) will be also referred to as “CHN 110”.

As described above, the storage system 600 is equipped with the channelcontrollers 1 to 4 (110) which can individually provide services as NASsto one storage system 600, and thus NAS services which have beenhitherto individually operated by independent computers can becollectively operated in one storage system 600. Accordingly, thecentralized management of the storage system 600 is possible, andmaintenance works, such as various kinds of setting/control, troublemanagement, version management, etc., can be efficiently performed.

The channel controllers 1 to 4 (110) of the storage device controller100 according to this embodiment is implemented by integrally unitizedhardware formed on a circuit board 180 and software, such as anoperating system (hereinafter referred to as “OS”), implemented by thehardware, application programs operating on the OS, etc. as describedlater. As described above, in the storage system 600 of this embodiment,the functions which have been hitherto mounted as a part of hardware areimplemented by the software. Therefore, according to the storage system600 of this embodiment, a flexible system operation can be performed,and more delicate services can be provided in response to variousrapidly-varying users' needs.

The information processing devices 3 and 4 (200) are connected to thestorage device controlling device 100 through SAN 500. SAN 500 is anetwork through which data is transmitted/received between the storagedevice controlling device 100 and the information processing devices 3,4 (200) on a block basis, the block serving as a management unit of datain a storage area provided by the disk driving device 300. Thecommunications between the information processing devices 3, 4 (200) andthe storage device controller 100 through SAN 500 are generally carriedout according to a fibre channel protocol. A block-basis data accessrequest (hereinafter referred to as “block access request”) istransmitted from each of the information processing devices 3, 4 (200)to the storage system 600 according to the fibre channel protocol.

A SAN-adapted backup device 900 is connected to SAN 500. The SAN-adaptedbackup device 900 communicates with the storage device controller 100through SAN 500 to store the backup data consisting of data stored inthe disk driving device 300.

The storage device controller 100 is equipped with channel controllers 5to 6 (110). The storage device controller 100 communicates with theinformation processing devices 3 to 4 (200) and the SAN-adapted backupdevice 900 through SAN 500 by the channel controllers 5 to 6 (110). Thechannel controllers 5 to 6 will be also referred to as “CHF”.

The information processing device 5 (200) is connected to the storagedevice controller 100 without passing through any network such as LAN400, SAN 500 or the like. The information processing device 5 (200) maybe a main frame computer. The communications between the informationprocessing device 5 (200) and the storage device controller 100 arecarried out according to a communication protocol such as FICON (FibreConnection) (registered trademark), ESCON (Enterprise System Connection)(registered trademark), ACONARC (Advanced Connection Architecture)(registered trademark), FIBARC (Fibre Connection Architecture)(registered trademark) or the like. A block access request istransmitted from the information processing device 5 (200) to thestorage system 600 according to these communication protocols.

The storage device controller 100 communicates with the informationprocessing device 5 (200) under control of the channel controllers 7 and8 (110). The channel controllers 7 and 8 (110) will also hereinafter bereferred to as “CHA”.

SAN 500 is connected to another storage system 610 that is set up at aremote place (secondary site) from a setup place of the storage system600 to protect data when a disaster occurs or the like. The storagesystem 610 is used as a device at a data copy destination in areplication or remote copy function. The storage system 610 may beconnected to the storage system 600 through a communication line, suchas an ATM or the like, in place of SAN 500. In this case, as the channelcontroller 110 is provided with an interface (channel extender) to usethe above communication line.

As described above, in the storage system 600 of this embodiment, CHN110, CHF 110 and CHA 110 can be mounted in the storage system 600 as soto coexist with one another. Accordingly, a storage system that isconnected to different kinds of networks can be implemented.Specifically, this is a SAN-NAS integral storage system in which thestorage system 600 is connected to a LAN 400 by using a CHN 110 and alsois connected to a SAN 500 by using a CHF 110.

[Storage Volume]

The disk driving device 300 is equipped with many disk drives, and thusit provides a large capacity storage area to the information processingdevice 200. The disk driving device 300 may be designed so that a discarray is constructed by plural disk drives. In this case, the storagearea provided to the information processing device 200 may be providedfrom plural disk drives managed by a RAID system.

The storage device controlling device 100 and the disk driving device300 may be directly connected to each other as shown in FIG. 1, or theymay be connected to each other through a network. Furthermore, the diskdriving device 300 may be constructed integrally with the storage devicecontroller 100.

The LU 310 equipped to the disk driving device 300 contains a user LU310 that is accessible from the information processing device 200, asystem LU 310 that is used to control the channel controllers 110, etc.An operating system executed in the CHN 110 is also stored in the systemLU 310.

[Storage Device Controlling Device]

The storage device controller 100 is equipped with channel controllers110, a shared memory 120, a cache memory (first memory) 130, a diskcontroller 140, a management terminal 160 and a connecting portion 150.

The channel controller 110 is equipped with a communication interfacefor making communications with the information processing device 200,and it has a function of transmitting/receiving a data input/outputcommand, etc. to/from the information processing device 200. Forexample, the CHN 110 receives a file access request from the informationprocessing devices 1 to 3 (200). It finds the storage address of thefile, the data length, etc. and outputs an I/O request corresponding tothe file access request to access the disk driving device 300, wherebythe storage system 600 can provide the information processing devices 1to 3 (200) with services as a NAS. The I/O request contains the headaddress of the data, the data length, the access type, such as readingor writing, etc. In the case of the data writing, the I/O request maycontain writing data. The output of the I/O request is carried out bythe processor 1 (first processor) 119. CHF 110 accepts a block accessrequest based on the fibre channel protocol from the informationprocessing devices 3 to 4 (200), whereby the storage system 600 canprovide the information processing devices 3 to 4 (200) with high-speedaccessible data storage services. Furthermore, the CHA 110 accepts ablock access request based on a protocol such as FICON, ESCON, ACONARC,FIBARC or the like from the information processing device 5 (200),whereby the storage system 600 can also provide a main frame computersuch as the information processing device 5 (200) with data storageservices.

Each channel controller 110 is connected to the management terminal 160through an internal LAN 151, whereby micro-programs, etc. executed inthe channel controllers 110 and the disk controllers 140 can betransmitted from the management terminal 160 and installed. Theconstruction of the channel controllers 110 will be described later.

The connecting portion 150 mutually connects the channel controllers110, the shared memory 120, the cache memory 130 and the diskcontrollers 140 to one another. The communications of data and commandsamong the channel controllers 110, the shared memory 120, the cachememory 130 and the disk controllers 140 are carried out through theconnecting portion 150. The connecting portion 150 is provided as across-bar switch, for example. The channel controllers 110 are mutuallyconnected to one another by the connecting portion 150, whereby thecommunication performance among the channel controllers 110 can be moregreatly enhanced as compared with the construction in which NAS serversoperating on individual computers are mutually connected to one anotherthrough LAN 400. Furthermore, this construction makes possible ahigh-speed file sharing function and high-speed failed-over.

The shared memory 120 and the cache memory 130 are storage memoriesshared by the channel controllers 110 and the disk controllers 140. Theshared memory 120 is mainly used to store control information, commands,etc., and the cache memory 130 is mainly used to store data.

For example, when a data input/output command received from theinformation processing device 200 by some channel controller 110 is awriting command, the channel controller 110 concerned writes the writingcommand into the shared memory 120, and, at the same time, it writes thewriting data received from the information processing device 200 intothe cache memory 130. The disk controller 140 monitors the shared memory120, and when it detects that the writing command is written into theshared memory 120, it reads out the writing data from the cache memory130 according to the command concerned and writes the data into the diskdriving device 300.

When a data input/output command received from the informationprocessing device 200 by some channel controller 110 is a read-outcommand, it is investigated whether data to be read out exists in thecache memory 130. Here, if the data exists in the cache memory 130, thechannel controller 110 transmits the data concerned to the informationprocessing device 200. On the other hand, when the data to be read outdoes not exist in the cache memory 130, the channel controller 110concerned writes a read-out command into the shared memory 120, and alsomonitors the shared memory 120. The disk controller 140, which detectsthat the read-out command has been written into the shared memory 120,reads out the read-target data from the disk driving device 300 andwrites the data into the cache memory 130, and it also writes this factinto the shared memory 120. When the channel controller 110 detects thatthe data to be read out has been written into the cache memory 130, ittransmits the data concerned to the information processing device 200.

As described above, data is transmitted/received between the channelcontroller 110 and the disk controller 140 through the cache memory 130.

In addition to the construction in which the data writing/readinginstruction from the channel controller 110 to the disk controller 140may be indirectly carried out through the shared memory 120, the datawriting/reading instruction from the channel controller 110 to the diskcontroller 140 may be directly carried out through no shared memory 120.

Furthermore, by providing the channel controller 110 with the functionof the disk controller 140, the channel controller 110 can read/writedata stored in the disk driving device 300.

The disk controller 140 controls the disk driving device 300. Forexample, the channel controller 110 writes data into the disk drivingdevice 300 according to the data writing command received from theinformation processing device 200 as described above. The diskcontroller 140 converts the logical-address-indication based I/O requestto LU 310 to the physical-address-indicates based I/O request to aphysical disk. Furthermore, when the physical disk in the disk drivingdevice 300 is managed by a RAID system, data access based on the RAIDconfiguration is carried out. The disk controller 140 performs copymanagement control and backup control on data stored, in the diskdriving device 300. Furthermore, the disk controller 140 also controlsstorage of a copy of data of the storage system 600 at a primary site toanother storage system 610 set up at a secondary site (replicationfunction or remote copy function), etc. in order to prevent data losswhen a disaster occurs (disaster recovery).

Each disk controller 140 is connected to the management terminal 160 andalso to the internal LAN 151, and it is enabled to make mutualcommunications with them. Accordingly, micro-programs, etc. to beexecuted in the disk controllers 140 can be transmitted from themanagement terminal 160 and installed. The construction of the diskcontroller 140 will be described later.

In this embodiment, the shared memory 120 and the cache memory 130 areequipped independently of the channel controllers 110 and the diskcontrollers 140, however, this embodiment is not limited to this mode.It is also preferable that the shared memory 120 or the cache memory 130is dispersively equipped to each of the channel controllers 110 and thedisk controllers 140. In this case, the connecting portion 150 canmutually connect the channel controllers 110 and the disk controllers140, each having the dispersively-equipped shared memory 120 or cachememory 130.

[Management Terminal]

The management terminal 160 is a computer for maintaining/managing thestorage system 600. Setting of the physical disk construction in thedisk driving device 300, setting of the LU 310, installation ofmicro-programs to be executed in the channel controllers 110 and thedisk controllers 140, etc. can be performed by operating the managementterminal 160. Here, expansion/reduction of the physical disk, a changeof the RAID construction (the change from RAID1 to RAID5, etc.) can beperformed as a setting of the physical disk construction in the diskdriving device 300. Furthermore, a check of the operating state of thestorage system 600, the specification of a trouble site, installation ofthe operating system to be executed in the channel controllers 110, etc.can be also performed from the management terminal 160. Such setting andcontrol are carried out by an operator or the like while a Web pageprovided from a Web server operating in the management terminal 160 isused as a user interface. The operator or the like can set targets orthe contents to be trouble-monitored, set a trouble notificationdestination, etc. by operating the management terminal 160.

The management terminal 160 may be designed in such a style as to becontained in the storage device controlling device 100 or equippedexternally. Furthermore, the management terminal 160 may be a computerwhich exclusively maintains/manages the storage device controllingdevice 100 and the disk driving device 300, or it may be a generalcomputer which is brought with the maintenance/management function.

FIG. 4 is a block diagram showing the construction of the managementterminal 160.

The management terminal 160 is equipped with a CPU 161, a memory 162, aport 163, a recording medium reading device 164, an input device 165, anoutput device 166 and a storage device 168.

The CPU 161 controls the overall management terminal 160. It executes aprogram 162 c stored in the memory 162 to implement the function as theWeb server. In the memory 162 are stored a physical disk managementtable 162 a, an LU management table 162 b and the program 162 c.

The physical disk management table 162 a is a table for managing thephysical disk (disk drive) equipped to the disk driving device 300. Thephysical disk management table 162 a is shown in FIG. 5. Only thephysical disks having the disk numbers #001 to #006 out of the manyphysical disks equipped to the disk driving device 300 are shown in FIG.5. The capacity, the RAID construction and the use status are shown foreach physical disk.

The LU management table 162 b is a table for managing the logical volume310 logically set on the physical disk. The LU management table 162 b isshown in FIG. 6. Only the LUs 310 having the LU numbers #1 to #3 out ofmany LUs 310 set on the disk driving device 300 are shown in FIG. 6. Thephysical disk number, the capacity and the RAID construction are shownfor each LU 310.

The recording medium reading device 164 is a device for reading outprograms and data recorded in a recording medium 167. The programs ordata read out are stored in the memory 162 or the storage device 168.Accordingly, the program 162 c recorded in the recording medium 167 canbe read out from the recording medium 167 by using the recording mediumreading device 164, it is and stored into the memory 162 or the storagedevice 168. A flexible disk, CD-ROM, a semiconductor memory or the likemay be used as the recording medium 167. The recording medium readingdevice 164 may be designed to be contained in the management terminal160 or equipped at the external side. The recording device 168 maybe ahard disk device, a semiconductor storage device or the like. The inputdevice 165 is used to effect data input to the management terminal 160by an operator or the like. For example, a keyboard, a mouse or the likeis used as the input device 165. An output device 166 may be a devicefor outputting information to the outside, and a display, a printer orthe like is used as the output device 166. The port 163 is connected tothe internal LAN 151, and the management terminal 160 can communicatewith the channel controllers 110, the disk controllers 140, etc. throughthe port 163. The port 163 may be also connected to LAN 400 and atelephone line.

[Outlook View]

Next, FIG. 2 shows the outlook construction of the storage system 600according to this embodiment, and FIG. 3 shows the outlook constructionof the storage device controlling device 100.

As shown in FIG. 2, the storage system 600 of this embodiment isdesigned in such a style that the storage device controlling device 100and the disk driving device 300 are respectively accommodated in therespective housings. The housings of the disk driving device 300 aredisposed at both the sides of the storage device controller 100.

The storage device controller 100 is equipped with the managementterminal 160 at the center portion of the front face thereof. Themanagement terminal 160 is covered by a cover, and the managementterminal 160 is allowed to be used by opening the cover as shown in FIG.3. The management terminal 160 shown in FIG. 3 is designed as aso-called lap top personal computer, however, it may be designed as anytype of computer.

At the lower side of the management terminal 160, there are slots inwhich the channel controllers ho, the disk controllers 140, the cachememory 130, the shared memory 120 and the connecting portion 150 aremounted. Each of the channel controllers 110, the disk controllers 140,the cache memory 130, the shared memory 120 and the connecting portion150 is designed in the form of a board so as to have a circuit board,and these boards are mounted in the respective slots. Each slot isequipped with guide rails for mounting the corresponding board. Byinserting each board into the slot along the guide rails, the channelcontrollers 110, the disk controllers 140, the cache memory 130, theshared memory 120 and the connecting portion 150 can be mounted in thestorage device controller 100. Furthermore, the boards mounted in therespective slots can be removed by pulling them out in the frontwarddirection along the guide rails. A connector for electrically connectingeach board to the storage device controller 100 is equipped at the frontsurface portion in the depth direction of each slot. The channelcontrollers 110 include CHN 110, CHF 110 and CHA 110, and all thechannel controllers 110 also can be mounted in the same slot becausethey are compatible with one another in size, connector position,connector pin arrangement, etc.

The plural channel controllers 110 mounted in the slots are the samekinds of plural channel controllers 110 and they form a cluster 180. Forexample, a cluster 180 can be constructed by pairing two CHNs 110. Withthe construction of clusters 180, even when trouble occurs in a channelcontroller 110 belonging to some cluster, another channel controller 110belonging to the same cluster can take over the processing which hasbeen carried out by the channel controller 110 having trouble (fail-overcontrol). FIG. 12 shows an example in which the cluster 180 isconstructed by two CHNs 110.

As described above, the channel controllers 110, the disk controllers140, the cache memory 130, the shared memory 120 and the connectingportion 150 are constructed as boards which are mountable in respectiveslots, and each board may be designed to have plural circuit boards.That is, the board may comprise plural circuit boards. When circuitboards are mutually connected to one another to form a unit and thesecircuit boards can be integrally mounted in a slot of the storage devicecontroller 100, these circuit boards are contained in the concept of aboard.

The storage device controller 100 is equipped with fans 170 forradiating heat generated from the channel controllers 110, etc. The fans170 are equipped at the upper surface portion of the storage devicecontroller 100, and also equipped at the upper side of the slots.

Conventional devices which are manufactured as SAN-adapted products maybe used as the storage device controller 100 and the disk driving device300. Particularly when the connectors of CHFs 110 are designed to becompatible with the connectors of CHAs 110 and CHFs 110 as describedabove so that they can be mounted in the slots formed in a conventionalhousing, the conventional device can be more simply used. That is, thestorage system 600 of this embodiment can be easily constructed byutilizing existing products.

[Channel Controller]

The storage system 600 according to this embodiment accesses file accessrequests from the information processing devices 1 to 3 (200) undercontrol of a CHN 110, as described above, and it supplies the servicesas a NAS to the information processing devices 1 to 3 (200).

FIG. 7 shows the construction of the CHN 110. As shown in FIG. 7, a CHN110 is constructed as one unified board having a circuit board(s) 118.The CHN 110 is constructed to have one or plural circuit boards 118. Onthe circuit board 118 there are a processor 1 (119), a processor 2(second processor) 112, a DMA (data transfer device) 114, a memory 1(third memory) 117, a memory 2 (second memory) 113, a memory controller1 (111), a memory controller 2 (111) and a connector 116. The processor1 (119), the processor 2 (second processor) 112, DMA (data transferdevice) 114, the memory controller 1 (111) and the memory controller 2(111) are connected to one another through a PCI (Peripheral ComponentInterconnect) bus so that they can communicate with one another.However, all parts are not necessarily required to be connected to oneanother through the PCI bus, and some or all of the connections may beset to conform with other standards.

The processor 2 (112), the memory 2 (113) and the memory controller 2(111) provide the communication interface function for communicatingwith the information processing device 200, and function as a fileaccess processor. In the case of CHN 110, it receives a file accessrequest transmitted from the information processing device 200 accordingto the TCP/IP protocol, for example, and controls thetransmission/reception of data. The connector 116 connected to thememory controller 2 (111) is used to communicate with the informationprocessing device 200.

The processor 2 (112) effects control to make the CHN 110 function as aNAS by executing various programs stored in the memory 2 (113).

Various programs and data are stored in the memory 2 (113). For example,data transmitted/received to/from the information processing device 200is stored in the memory 2. Furthermore, various kinds of programs, suchas meta data 730 and a lock table 720 shown in FIG. 9, an NAS manager706, etc. are stored. The meta data 730 is information generated inconnection with files managed by the file system. The meta data 730contains information for specifying the storage places of the files,such as the addresses and data size on the LU 310 in which the data ofthe files is stored. The meta data 730 may contain the capacities,owners, renewal times, etc. of the files. Furthermore, the meta data 730may be generated not only in connection with the files, but also inconnection with the directories. FIG. 13 show an example of the metadata 730. The metal data 730 is also stored on each LU 310 on the diskdriving device 300.

The lock table 720 is a table for exclusively controlling the fileaccess from the information processing devices 1 to 3 (200). Throughexclusive control, the information processing devices 1 to 3 (200) canjointly own the files. FIG. 14 shows the lock table 720. As shown inFIG. 14, the lock table 720 is classified into a file lock table 721 andan LU lock table 722. The file lock table 721 is a table indicatingwhether the lock is applied for every file or not. When a file is openedby some information processing device 200, the file concerned is locked.Any access from the other information processing devices 200 to thelocked file is prohibited. The LU lock table 722 is a table indicatingwhether the lock is applied for every LU 310 or not. When access to someLU 310 is made by some information processing device 200, the LU 310concerned is locked. Any access of the other information processingdevices 200 to the locked LU 310 is prohibited.

The storage address (storage position) of the data stored in the memory2 (113) is managed by the processor (112).

The processor 1 (119), the memory 1 (117), DMA 114 and the memorycontroller 1 (111) transmit/receive data or commands to/from the diskcontrollers 140, the cache memory 130, the shared memory 120 and themanagement terminal 160. The processor 1 (119) instructs DMA 114 totransfer the data stored in the memory 2 (113) to the cache memory 130and transfer the data stored in the cache memory 130 to the memory 2(113). That is, the data transfer between the memory 2 (113) and thecache memory 130 is carried out by DMA 114.

The processor 1 (119) outputs to the disk controller 140, through theshared memory 120, the block access request corresponding to the fileaccess request received from the information processing device 200 bythe processor 2 (112). The processor 1 (119) manages the storageaddresses (storage positions) of data stored in the cache memory 130 andthe storage addresses (storage positions) of data stored in the memory 1(117).

The data transfer carried out between the cache memory 130 and thememory 2 (113) will be described in detail later.

Next, the hardware construction of the CHF 110 and CHA 110 is shown inFIG. 8. As in the case of the CHN 110, each of the CHF 110 and CHA 110is constructed as one unified board having a circuit board(s) 118. LikeCHN 110, each of the CHA 110 and CHF 110 may be constructed to haveplural circuit boards. CHF 110 and CHA 110 are designed to be compatiblewith CHN 110 in size, the position of the connector 116, the pinarrangement of the connector 116, etc.

A processor 1 (119), a protocol chip 115, a DMA 114, a memory 1(117), amemory 2 (113), a memory controller 1 (111), a memory controller 2 (111)and a connector 116 are formed on the circuit board 118 of the ° CHF 110and CHA 110. The processor 1 (119), the protocol chip 115, the DMA 114,the memory controller 1 (111) and the memory controller 2 (111) areconnected to one another through a PCI (peripheral ComponentInterconnect) bus so that communications can be carried out there among.However, all of the parts are not necessarily required to be connectedto one another through the PCI bus, and some or all of the connectionsmay be designed to conform with another standard.

The protocol chip 115, the memory 2 (113) and the memory controller 2(111) provide the communication interface function for communicatingwith the information processing device 200. In the case of CHF 110, itreceives the block access request transmitted from the informationprocessing device 200 according to the fibre channel protocol. In thecase of CHA 110, it receives the block access request transmitted fromthe information processing device 200 according to a protocol such asFICON (registered trademark), ESCON (registered trademark), ACONARC(registered trademark), FIBARC (registered trademark) or the like. Theconnector 116 connected to the memory controller 2 (111) is a connectorfor connecting with the information processing device 200. In the caseof CHF 110, it is a connector connectable to the SAN 500, and it isadapted to fibre channels. In the case of CHA 110, it is a connectorconnectable to the information processing device 5, and it is adapted toFICON (registered trademark), ESCON (registered trademark), ACONARC(registered trademark), FIBARC (registered trademark), etc.

In the memory 2, there are stored data transmitted/received to/from theinformation processing device 200, for example. In the case of the CHF110 or CHA 110, the storage addresses (storage positions) of data storedin the memory 2 (113) are managed by the processor 1 (119).

The processor 1 (119), the memory 1 (117), the DMA 114 and the memorycontroller (111) transmit/receive data and commands to/from the diskcontrollers 140, the cache memory 130, the shared memory 120 and themanagement terminal 160. The processor 1 (119) instructs the DMA 114 totransmit the data stored in the cache memory 130 to the memory 2 (113).That is, the data transfer between the memory 2 (113) and the cachememory 130 is carried out by DMA 114.

The processor 1 (119) outputs the block access request received from theinformation processing device 200 through the shared memory 120 to thedisk controller 140. Furthermore, the processor 1 (119) manages thestorage addresses (storage positions) of the data stored in the cachememory 130 and the storage addresses (storage positions) of the datastored in the memory 1 (117). That is, in the case of the CHA 110 or CHF110, the data transfer between the memory 2 (113) and the cache memory130 is carried out on the basis of the storage positions of the data ofthe cache memory 130 and the memory 2 (113) managed by the processor 1(119).

[Disk Controller]

The construction of the disk controller 140 is shown in FIG. 10. Thedisk controller 140 is equipped with an interface portion 141, a memory143, a CPU 142, a NVRAN (nonvolatile random-access memory) 144, and aconnector 145, and these parts are integrally formed as a unit.

The interface portion 141 is equipped with a communication interface forcommunicating with the channel controllers 110, etc. through theconnecting portion 150, and a communication interface for communicatingwith the disk driving device 300.

The CPU 142 controls the overall disk controller 140, and it alsocommunicates with the channel controller 110, the disk driving device300 and the management terminal 160. The various programs stored in thememory 143 and NVRAM 144 are executed by the CPU 142 to implement thefunction of the disk controller 140 according to this embodiment. Thefunction implemented by the disk controller 140 includes the control ofthe disk driving device 300, the RAID control, the copy management,backup control and remote copy control, etc. of data stored in the diskdriving device 300.

The NVRAN 144 is a nonvolatile memory for storing programs used tocontrol the CPU 142. The contents of the programs' stored in the NVRAN144 can be written/rewritten on the basis of an instruction from the NASmanager 706.

Furthermore, the disk controller 140 is equipped with a connector 145.The connector 145 is engaged with the connector at the storage devicecontroller 100 side, whereby the disk controller 140 is electricallyconnected to the storage device controller 100.

[Software Configuration]

The software configuration of the storage system 600 according to thisembodiment is shown in FIG. 11.

Software such as a RAID manager 708, a volume manager 707, an SVP(SerVice Processor) manager 709, a file system program 703, a networkcontrol program 702, a backup management program 710, a troublemanagement program 705, an NAS manager 706, etc. operate on an operatingsystem 701.

The RAID manager 708 operating on the operating system 701 provides thesetting function of parameters for the RAID controller 740 which iscarried out in the disk controller 140, and the function of controllingthe RAID controller 740. The RAID manager 708 accepts the operatingsystem 701 and the other applications operating on the operating system701, or parameters and control instruction information from themanagement terminal 160 to set the accepted parameters in the RAIDcontroller 740 and transmit the control command corresponding to theRAID controller instruction information.

The volume manager 707 supplies the file system block 703 with a virtuallogic volume achieved by further virtualizing the LU 310 supplied fromthe RAID controller 740. One virtual logic volume comprises one or morelogic volumes.

The main function of the file system program 703 is to manage theassociation between a file name indicated in a file access requestreceived by the network control program 702 and the address on thevirtual logic volume at which the file name concerned is stored. Forexample, the file system program 703 specifies the address on thevirtual logic volume which corresponds to the file name indicated in thefile access request.

The network control program 702 comprises two file system protocols,including NFS (Network File System) 711 and samba 712. NFS 7,11 acceptsa file access request from a UNIX (registered trademark) typeinformation processing device 200 in which NFS 711 operates. Samba 712accepts a file access request from a Windows (registered trademark) typeinformation processing device 200 in which CIFS (Common Interface FileSystem) 713 operates.

The NAS manager 706 is a program to check and set the operating statusof the storage system 600. The NAS manager 706 also functions as a webserver, and it provides the information processing device 200 with a Webpage for performing the setting and control of the storage system 600from the information processing device 200. The NAS manager 706 receivesthe data relevant to the setting and control which are transmitted fromthe information processing device 200 in response to the operation ofthe Web page, and executes setting and control corresponding to thedata. Accordingly, various setting and control of the storage system 600can be performed from the information processing devices 1 to 3 (200).

The backup management program 710 is a program for backing up the datastored in the disk driving device 300 via LAN 400 or SAN 500.

The trouble management program 705 is a program for performing thefail-over control described above between the channel controllers 110constituting the cluster 180.

The SVP manager 709 supplies the management terminal 160 with variousservices, in response to a request from the management terminal 160. Forexample, it supplies the management terminal 160 with various settingcontents concerning the storage system 600, such as the setting contentof LU 310, the setting content of RAID, etc., and reflects the variouskinds of settings relevant to the storage system 600 which are inputfrom the management terminal 160.

The security management program 716 implements a computer virusdetecting function, a function for monitoring of invasion of a computervirus, a management function for renewal of a computer virus detectingprogram, a function of excluding an infected computer virus, a fire wallfunction, etc.

[Data transfer by DMA]

Next, data transfer between the memory 2 (113) and the cache memory 130in CHN 110 according to this embodiment will be described.

As shown in FIG. 16, the memory 2 has a data area and a script area.Data to be transferred to the cache memory 130 or data transferred fromthe cache, memory 130 are stored in the data area. The storage positionof each data stored in the data area, the size (area length) of thestorage area of each data, etc. are stored in the script area of thememory 2 (113) as a script for the processor 2 (second data transferinformation) in association with each data. The script for the processor2 has respective columns for “script identifier”, “area head address”,“area length” and “sequential Flag”. The “script identifier” indicatesan identification number allocated for every script for the processor 2.The “area head address” indicates the storage address of data stored inthe data area. The “area length” indicates the size of the storage areaof the data. The “sequential Flag” is a flag set when plural data storedin the data area are required to be transferred as a lump. These scriptsfor the processor 2 stored in the memory 2 (113) are set by theprocessor 2 (112), and written in the script area of the memory 2 (113).

Furthermore, data to be transferred to the memory 2 (113) or datatransferred from the memory 2 (113) are stored in the data area of thecache memory 130 as shown in FIG. 18. The storage position of each datastored in the data area, the size (area length) of the storage area ofeach data, etc. are stored in the script area of the memory 1 (117) as ascript for the processor 1 (first data transfer information) inassociation with each data. The script for the processor 1 is equippedwith respective columns for “script identifier”, “area head address”,“area length” and “sequential Flag”. The meaning of each column is thesame as the script for the processor, 2 in the memory 2 (113).

The scripts for the processor 1 stored in the memory 1 (117) are set bythe processor 1 (119), and written into the scrip area of the memory 1(117). Next, the construction of the DMA 114 for controlling the datatransfer between the memory 1 (113) and the cache memory 130 on thebasis of each script will be described with reference to FIG. 15.

The DMA 114 has a DMA controller 801, a PCI interface 802, a transferstart register 803, a transfer register 804, an initializing register805 and a script register 806.

The DMA controller 801 controls the whole DMA 114. For example, it readsout the scripts described above, controls the data transfer, outputs anend status (the transfer result of data), etc. The DMA controller 801may be constructed by only hardware or by a combination of hardware andsoftware.

The PCI interface 802 is a communication interface for communicatingwith the memory controller 111, etc. through the PCI bus. However, whenthe connection between the DMA 114 and the memory controllers 111, etc.is conformed with standards other than PCI, the PCI interface 802 may bea communication interface conformed with the respective other standards.

The transfer start register 803 is equipped with each of the registersfor “request transfer length”, “transfer direction”, “processor 2starting script number” and “processor 1 starting script number”.

The “request transfer length” register describes the total data lengthof data transferred between the memory 2 (113) and the cache memory 130.The request transfer length is determined on the basis of the fileaccess request received from the information processing device 200. Forexample, when the processor 2 (112) receives a writing request of dataof 8 kilo bytes (kB) from the information processing device 200, 8 kB isstored in the “request transfer length” register. As will be describedin detail later, the request transfer length is temporarily transmittedfrom the processor 2 (112) for receiving the file access request to theprocessor 1 (119), and then it is written into the transfer startregister 803 of the DMA 114 by the processor 1 (119) when the processor1 (119) starts data transfer to the DMA 114.

The “transfer direction” register describes whether the data transfer isdirected from the memory 2 (113) to the cache memory 130 or from thecache memory 130 to the memory 2 (113). The transfer direction isdetermined on the basis of the file access request received from theinformation processing device 200 by the processor 2 (112). For example,when the processor 2 receives a data writing request from theinformation processing device 200, the transfer direction is thetransfer from the memory 2 (113) to the cache memory 130. When theprocessor 2 (112) receives a data reading request from the informationprocessing device 200, the transfer direction is from the cache memory130 to the memory 2 (113). As will be described in detail later, as inthe case of the request transfer length, the transfer direction istemporarily transmitted from the processor 2 (112) for receiving thefile access request to the processor 1 (119), and then it is writteninto the transfer start register 803 of DMA 114 by the processor 1 (119)when the processor 1 (119) starts the data transfer to DMA 114.

The identifier of the script for the processor 2 stored in the memory 2(113) is described in the “processor 2 starting script number”. The DMAcontroller 801 reads out from the memory 2 (113) the script for theprocessor 2 stored in the “processor 2 starting script number” register,and starts the data transfer. The processor 2 starting script number istemporarily transmitted from the processor 2 (112) for controlling thememory 2 (113) to the processor 1 (119), and then it is written into thetransfer start register 803 of the DMA 114 by the processor 1 (119) whenthe processor 1 (119) starts the data transfer to the DMA 114.Alternatively, when the sequential Flag is set in the script for theprocessor 2, the processor 2 starting script number is renewed by theDMA controller 801.

The identifier of the script for the processor 1 stored in the memory 1(117) is described in the “processor 1 starting script number”. The DMAcontroller 801 reads out from the memory 1 (117) the script for theprocessor 1 stored in the “processor 1 starting script number”, andstarts the data transfer. The processor 1 starting script number iswritten into the transfer start register 803 of DMA 114 by the processor1 (119) when the processor 1 (112) for controlling the cache memory 130starts the data transfer to DMA 114. Alternatively, when the sequentialFlag is set in the script for the processor 1, the processor 1 startingscript number is renewed by the DMA controller 801.

The transfer register 8,04 is equipped with respective registers for“transfer unit”, “transfer source address”, “transfer destinationaddress” and “residual transfer length”.

The “transfer unit” register describes the data transfer length in onedata transfer. The data transfer length in one data transfer iscalculated by the DMA controller 801. As will be described in detaillater, the transfer unit is determined by the DMA controller 801according the flow shown in FIG. 22.

The “transfer source address” register indicates the storage position ofdata before transfer. The transfer source address is determined on thebasis of the description of the transfer direction and the script forthe processor 1 or the script for the processor 2. During the datatransfer, the value of the “transfer source address” register isproperly incremented or decremented by the DMA controller 801 with theprogress of the data transfer.

The “transfer destination address” register indicates the storageposition of data-after transfer. The transfer destination address isdetermined on the basis of the description of the transfer direction andthe script for the processor 1 or the script for the processor 2. Duringthe data transfer, the value of the “transfer destination address”register is properly incremented or decremented by the DMA controller801 with the progress of the data transfer.

The “residual transfer length” register indicates the value achieved bysubtracting the transferred data transfer length from the requesttransfer length. The residual transfer length is properly renewed by theDMA controller 801 with the progress of the data transfer.

The initializing register 805 has respective registers for “script areahead address for the processor 2”, “script number for the processor 2”,“script size for the processor 2”, “script area head address for theprocessor 1”, “script number for the processor 1” and “script size forthe processor 1”. These values of the initializing register 805 may beread out from the NVRAM equipped to CHN 110 by the DMA controller 801when the channel controllers 110 are powered on and reset.

The “script area head address for the processor 2” indicates the headaddress of the script area in the memory 2 (113). That is, it indicatesthe address at which the script for the processor 2 is stored.

The “script number for the processor 2” indicates the number of scriptsfor the processor 2. It is equal to N+1 in the case of FIG. 16.

The “script size for the processor 2” indicates the size of the scriptfor the processor 2. When the size of the script for the processor 2 isfixed as described above, the storage address of the script for targetprocessor 2 based on the head address of the script area can becalculated by specifying the identifier of the script for the processor2.

Each of the “script area head address for the processor 1” register, the“script number for the processor 1” register and the “script size forthe processor 1” register is the same as the script for the processor 2.

The script register 806 has respective registers for “execution-scriptnumber for the processor 2”, “effective area length for the processor2”, “execution script number for the processor 1” and “effective arealength for the processor 1”.

The “execution script number for the processor 2” register indicates theidentifier of the script for the processor being executed at present.The execution script number for the processor 2 is set by the DMAcontroller 801.

The “effective area length for the processor 2” register indicates avalue achieved by subtracting the transferred data size from the arealength described in the column of the area length of the script for theprocessor 2, and it is properly decremented by the DMA controller 801with the progress of the data transfer.

The “execution script number for the processor 1” and the “effectivearea length for the processor 1” are the same as the “execution scriptnumber for the processor 2” register and the “effective area length forthe processor 2” register.

[Flow of Data Transfer]

Next, the processing flow of the data transfer carried out between thememory 2 (113) and the cache memory 130 will be described with referenceto the flowchart of FIGS. 19 to 23.

First, the processor 2 (112) secures the data area (S1000). When thefile access request transmitted from the information processing device200 is a writing request, the securement of the data area means thatwriting data is stored in the memory 2 (113). When the file accessrequest transmitted from the information processing device 200 is areading request, the securement means that a storage area for storingread-out data is secured in the memory 2 (113). Here, the data area tobe secured is not limited to one. This is because there may be a casewhere data relevant to one file access request must be divided intoplural parts and then stored in the memory 2 (113) under somedistribution situation of the data-storable area in the memory 2 (113).

Subsequently, the processor 2 (112) creates the script for the processor2 (S1001). The head address, the area length, etc. of the data areasecured in S1000 are stored as the script for the processor 2 in thescript area of the memory 2 (113). When plural data areas are secured inS1000, the script for the processor 2 is created for every data area. Atthis time, sequential Flags are set to manage, the respective scriptsfor the processor 2 in a lump.

Accordingly, the scripts for the processor 2 containing informationindicating the storabe positions of data in the memory 2 (113) arewritten in the memory 2 (113).

The processor 2 (112) transmits a data transfer request command to theprocessor 1 (119) (S1002). The data transfer request command containsthe identifier of the script for the processor 2 created in S101, therequest transfer length and the transfer direction. The request transferlength is the size of the data to be read/written, which is described inthe file access request.

The processor 1 (119) analyzes the data transfer request commandtransmitted from the processor 2 (112) (S1003) to recognize the numberof the script for the processor 2, the request transfer length and thetransfer direction.

Subsequently, the processor 1 (119) secures in the cache memory 130 thedata area having the size indicated by the request transfer length(S1004). In this case, there is also a case where plural data areas aresecured under some distribution situation of the storable memory spacein the cache memory 130.

The processor 1 (119) creates the script for the processor 1 inconnection with each data area secured in the cache memory 130 (S1005).When plural data areas are secured, sequential Flags are set to managethe respective scripts for the processor 1 in a lump.

Accordingly, the scripts for the processor 1 containing the informationindicating the storage positions of the data in the cache memory 130 arewritten in the memory 1 (117).

Thereafter, the processor 1 (119) transmits the transfer startinformation containing the request transfer length, the transferdirection, the identifier of the script for the processor 2 and theidentifier of the script for the processor 1 to the DMA 114, and itwrites this data into the transfer start register 803 of the DMA 114,whereby the processor 1 (119) starts DMA 114 (S1006).

At this time, the DMA 114 starts the DMA transfer processing (S1007).The DMA transfer processing will be described with reference to FIGS. 20to 23.

First, the DMA controller 801 achieves the script for the processor 1and the script for the processor 2 on the basis of the identifiers ofthe script for the processor 1 and the script for the processor 2 asdescribed in the transfer start information (S2000). The scripts areachieved as shown in FIG. 21.

The DMA controller 801 calculates the storage address of the script forthe processor 1 in the memory 1 (117) from the identifier of the scriptfor the processor 1 described in the transfer start informationtransmitted from the processor 1 (119) and the size of the script forthe processor 1 stored in the initializing register 805 on the basis ofthe transfer start information (S3000). When the storage address of thescript for the processor 1 can be calculated, the script for theprocessor 1 is subsequently read out from the storage address concernedin the memory 1 (117) (S3001). Here, the DMA controller 801 writes thearea head address described in the script for the processor 1 into thetransfer destination address or transfer source address column of thetransfer register 804 in accordance with the transfer direction. Thescript identifier described in the script for the processor 1 and thearea length described in the area length column are written in theexecution script number column for the processor 1 of the scriptregister 806 and the effective area length column for the processor 1,respectively (S3002).

Likewise, the DMA controller 801 calculates the storage address of thescript for the processor 2 in the memory 2 (113) from the identifier ofthe script for the processor 2 described in the transfer startinformation transmitted from the processor 1 (119) and the size of thescript for the processor 2 stored in the initializing register 805 onthe basis of the transfer start information (S3000). When the storageaddress of the script for the processor 2 can be calculated, the scriptfor the processor 2 is subsequently read out from the storage addressconcerned in the memory 2 (113) (S3001). Here, the DMA controller 801writes the area head address described in the script for the processor 2in the transfer source address column or transfer destination addresscolumn of the transfer register 804 in accordance with the transferdirection. The script identifier described in the script for theprocessor 2 of the script register 806 and the area length described inthe area length column are written in the execution script number columnfor the processor 2 of the script register 806 and the effective arealength column for the processor 2, respectively (S3002).

Subsequently, the DMA controller 801 determines the transfer unit(S2001). The transfer unit is determined according to the flow shown inFIG. 22.

First, the DMA controller 801 writes the residual transfer length intothe residual transfer column of the transfer register 804. The requesttransfer length is written at the start time of the transfer (S4000).

The minimum length of the effective area length of the processor 1, theeffective area length of the processor 2 and the residual transferlength is set as the transfer unit (S4001 to S4007).

The DMA controller 801 transfers to the transfer destination address thedata stored at the transfer source address stored in the transferregister 804 to the transfer destination address whose data amountcorresponds to only the data size of the transfer unit (S2002).

During execution of the transfer, the transfer source address, thetransfer destination address and the residual transfer length of thetransfer register 804 are successively renewed, and each of theeffective area length for the processor 2 and the effective area lengthfor the processor 1 in the script register 806 are successivelydecremented every data size of transferred data.

When any value of the effective area length for the processor 2, theeffective area for the processor 1 and the residual transfer length inthe script register 806 is equal to zero, the DMA controller 801 carriesout transfer end judgment processing (S2003).

The transfer end judgment processing is carried out according to theflow shown in FIG. 23.

First, the DMA controller 801 checks the residual transfer length of thetransfer register 804 (S5000). When the residual transfer length isequal to zero, transfer of all the data of the request transfer lengthhas been completed, and thus the processing goes to “No” to finish theprocessing.

On the other hand, when the residual transfer length is not equal tozero, at least one of the effective area length for the processor 1 andthe effective area length for the processor 2 is equal to zero. In thiscase, the script whose effective area length is equal to zero contains ascript to be next executed while the later script to be next executed islinked to the former script with a sequential Flag. Through theprocessing of S5001 to S5004, it is determined whether the script inwhich the script to be next executed exists is a script for theprocessor 1 or a script for the processor 2.

First, it is checked in S5001 whether the effective length for theprocessor 1 of the script register 806 is equal to zero or not. If it isequal to zero, the processing goes to “Yes”, and the start script numberfor the processor 1 is renewed in S5002. If it is not equal to zero, theprocessing goes to “No”.

Subsequently, it is checked whether the effective area length for theprocessor 2 is equal to zero or not (S5003). If it is equal to zero, theprocessing goes to “Yes”, and the start script number for the processor2 is renewed in S5004. If it is not equal to zero, the processing goesto “No”.

Subsequently, the DMA controller 801 executes the processing of S2000again. At this time, the DMA controller 801 reads out the start scriptnumber for the processor 1 of the transfer starting register 803 whichis renewed in S5002 or S5004, or the script indicated by the startscript for the processor 2. The DMA controller 801 carries out the DMAtransfer according to the script which is newly read out.

Finally, when the residual transfer length of the transfer register 804in the transfer end judgment processing in S2003 is equal to zero, theDMA controller 801 finishes the transfer processing. The DMA controller801 writes into the memory 1 (117) an end status in which the result ofthe transfer processing is described (S1008), and it transmits an endnotification to the processor 1 (119) (S1009). The end notification maybe transmitted on the basis of an interruption signal.

The processor 1 (119) reads out the end status from the, memory 1 (117),and it executes the processing corresponding to the content thereof(S1010). The processor 1 (119) transmits the end notification to theprocessor 2 (112).

When the file access request is a data read-out request, the processor 2(112) can read out the read-out data transmitted to the data area of thememory 2 (113) and transmit the data to the information processingdevice 200. When the file access request is a data writing request, thestorage area of the memory 2 (113) in which the writing data are storedmay be opened and used for other processing.

As described above, in the storage device controlling device 100according to this embodiment, the information such as the data storageposition, etc. of the cache memory 130 and the information such as thedata storage position, etc. of in the memory 2 (113) are written in thememory 1 (117) by the processor 1 (119). DMA 114 reads out thisinformation from the memory 1 (117) and carries out the data transfer.Accordingly, the idling time of the processor 1 (119) can be reduced,and the processor 1 (119) can be efficiently executed, so that the speedof the data reading/writing operating in response to the file accessrequest can be increased.

In the storage device controlling device 100 according to thisembodiment, the script for the processor 2 is stored in the memory 2(113). The processor 2 (112) transmits, not the script for the processor2, but the information indicating the storage position of the script forthe processor 2 to the processor 1 (119). With this operation, theamount of data transmitted from the inter-processor communication can bereduced, and the communication, time can be also reduced. Therefore, theDMA starting processing time can be shortened, and the speed of the datareading/writing operation carried out in response to the file accessrequest can be increased.

Furthermore, according to the storage device controlling device 100 ofthis embodiment, even when the data size of the transfer source and thedata size of the transfer destination are different from each other, thedata transfer can be controlled by DMA 114 without carrying out anycontrol by the processor 1 (119) or the processor 2 (112). Accordingly,the processing loads of the processor 1 (119) and the processor 2 (113)can be reduced, and the speed of the data reading/writing operationcarried out in response to the file access request from the informationprocessing device, 200 can be increased.

In the storage device controlling device 100 according to thisembodiment, the end status is not stored in the register of the DMA 114,but it is registered into the memory (117). The processor 1 (119) readsout the end status from the memory 1 (117), so that the reading time ofthe end status by the processor 1 (119) can be shortened. The idle timeof the processor 1 (119) can be reduced. Accordingly, the speed of thedata reading/writing operation carried out in response to the fileaccess request from the information processing device 200 can beincreased.

According to the storage device controlling device 100 of thisembodiment, the speed of the data reading/writing operation carried outin response to the file access request from the information processingdevice 200 can be increased, so that the speed of the datatransmission/reception to/from the storage system 610 set up at thesecondary site and the speed of the data transmission/reception to/fromthe backup devices 900, 910 can be increased. The processing performanceof the overall information processing system can be greatly enhancedirrespective of the scale of the information processing system using thestorage system 600.

In S1002, the data transfer request command transmitted from theprocessor 2 (112) to the processor 1 (119) may be set not to contain theidentifier of the script for the processor 2. In this case, theprocessor 2 (112) may be set so that the identifier of the script forthe processor 2 is stored at a predetermined storage portion in thememory 2 (113), and the DMA 114 reads out the identifier of the scriptfor the processor 2 from the storage position concerned before the DMAtransfer processing of S1007 is started.

In S1006, the transfer starting information transmitted from theprocessor 1 (119) to DMA 114 may be set not to contain the identifiersof the scripts for the processor 1 and for the processor 2. In thiscase, the processor 1 (112) may be set so that the identifier of thescript for the processor 1 and the identifier of the script for theprocessor 2 are stored at predetermined storage positions in the memory1 (117), and the DMA 114 can read out the identifier of the script forthe processor 1 and the identifier of the script for the processor 2 canbe read out from the storage positions concerned before the DMA transferprocessing of S1007 is started.

[Specific Example of DMA Transfer]

Next, the processing flow of the data transfer carried out between thememory 2 (113) and the cache memory 130 will be described with referenceto FIG. 24. In the example shown in FIG. 24, two 4 kB data stored in thememory 2 (113) are transferred as 2 kB data and 6 kB data to the 64 kBdata area of the cache memory 130.

In FIG. 19, the processor 2 (112) secures the data area (S1000). Thesecurement of the data are means that the writing data transmitted fromthe information processing device 200 is stored in the memory 2 (113).In the example of FIG. 24, the two 4 kB, data are stored in the memory 2(113).

Subsequently, the processor 2 (112) creates the script for the processor2 (S1001). Here, the processor 2 (112) creates two scripts for theprocessor 2 in connection with the two data stored in the memory 2(113). FIG. 24 shows the creation of the script 0 for the processor 2and the script 1 for the processor 2. “4 kB” is described as the arealength in the script 0 for the processor 2, and a sequential Flag isset. Furthermore, “4 kB” is described as the area length in the script 1for the processor 2, and no sequential Flag is set.

The processor 2 (112) transmits the data transfer request command to theprocessor 1 (119) (S1002). The data transfer command contains theidentifier of the script for the processor 2 created in S1001, therequest transfer length and the transfer direction. Here, “0” and “1”are transmitted as the identifier of the script for the processor 2, and“8 kB” is transmitted as the request transfer length. The transfer fromthe memory 2 (113) to the cache memory 130 is indicated as the transferdirection. The identifier of the script for the processor 2 transmittedfrom the processor 2 (112) to the processor 1 (119) may be set to beonly “0”.

Subsequently, the processor 1 (119) analyzes the data transfer commandtransmitted from the processor 2 (112) (S1003), thereby recognizing thenumber of the script for the processor 2, the request transfer lengthand the transfer direction.

The processor 1 (119) secures the data area having the size indicated bythe request transfer length in the cache memory 130 (S1004). In FIG. 24,a 2 kB data area and a 6 kB data area are secured.

The processor 1 (119) creates the script for the processor 1 (S1005).Here the processor 1 (119) creates two scripts for the processor 1 inconnection with the two data areas secured in the cache memory 130. InFIG. 24, it is shown that the script 0 for the processor 1 and thescript 1 for the processor 1 are created. “2 kB” is described as thearea length in the script 0 for the processor 1, and a sequential Flagis set. “6 kB” is described as the area length in the script 1 for theprocessor 1, and no sequential Flag is set.

Thereafter, the processor 1 (119) transmits to DMA 114 the transferstart information containing the request transfer length, the transferdirection, the identifier of the script 0 for the processor 2 and theidentifier of the script 0 for the processor 1, and writes this datainto the transfer start register 803 of DMA 114, thereby starting DMA114 (S1006).

At this time, DMA 114 starts the DMA transfer processing (S1007).

Specifically, the DMA controller 801 first achieves the script 0 for theprocessor 1 and the script 0 for the processor 2 (S2000). Theachievement of the scripts is carried out as shown in FIG. 21.

First, the DMA controller 801 calculates the storage address of thescript 0 for the processor 1 in the memory 1 (117) from the identifierof the script 0 for the processor 1 described in the transfer startinformation transmitted from the processor 1 (119) and the size of thescript for the processor 1 stored in the initializing register on thebasis of the transfer start information (S3000). When the storageaddress of the script 0 for the processor 1 is calculated, the script 0for the processor 1 is read out from the storage address concerned inthe memory 1 (117) (S3001). Here, the DMA controller 801 describes the#0 area head address described in the script 0 for the processor 1 inthe transfer destination address column of the transfer register 804.The script identifier “0” described in the script 0 for the processor 1and “2 kB” described in the area length column are written in theexecution script number column for the processor 1 and the effectivearea length column for the processor 1 in the script register 806,respectively (S3002).

Likewise, the DMA controller 801 calculates the storage address of thescript 0 for the processor 2 in the memory 2 (113) from the identifierof the script 0 for the processor 2 described in the transfer startinformation transmitted from the processor 1 (119) and the script sizefor the processor 2 stored in the initializing register on the basis ofthe transfer start information (S3000). When the storage address of thescript 0 for the processor 2 is calculated, the script 0 for theprocessor 2 is subsequently read out from the storage address concernedin the memory 2 (113) (S3001). Here, the DMA controller 801 sets the #0area head address described in the script 0 for the processor 2 into thetransfer source address column of the transfer register 804. The scriptidentifier 0 described in the script 0 for the processor 2 and “4 kB”described in the area length column are written in the execution scriptnumber column for the processor 2 and the effective area length columnfor the processor 2 in the script register 806, respectively (S3002).

Subsequently, the DMA controller 801 determines the transfer unit(S2001). The determination of the transfer unit is carried out accordingto the flow shown in FIG. 22.

First, the DMA controller 801 writes the request transfer length “8 kB”into the residual transfer length column of the transfer register 804(S4000).

Subsequently, the effective area length “2 kB” of the processor 1 in thescript register 806 is compared with the effective area length “4 kB” ofthe processor 2 in the script register 806 (S4001). In this case, thelatter effective length is large and thus the processing goes to “Yes”.Then, the effective area length “2 kB” of the processor 1 is comparedwith the residual transfer length “8 kB” (S4002). In this case, thelatter length is larger, and thus the processing goes to “Yes”.Accordingly, the effective length “2 kB” of the processor 1 isdetermined as the transfer unit (S4003).

The DMA controller 801 transfers to the transfer destination address thedata stored in the transfer source address stored in the transferregister 804, the data amount of the data thus transferred correspondingto only the data size of the transfer unit (S2002). That is, in thiscase, the data of the memory 2 (113) is transferred to the cache memory130 by only 2 kB.

During execution of the transfer, the transfer source address of thetransfer register 804, the transfer destination register and theresidual transfer length are successively renewed, and the effectivearea length for the processor 2 and the effective area length for theprocessor 1 in the script register 806 are successively reduced forevery data amount corresponding to the size of the transferred data.

When the effective area length for the processor 2, the effective areafor the processor 1 or the residual transfer length in the scriptregister 806 is equal to zero, the DMA controller 801 carries out thetransfer end judgment processing (S2003). At this time point, theeffective area length for the processor 1 in the script register 806 isequal to zero, the effective area length for the processor 2 is equal to2 kB, and the residual transfer length is equal to 6 kB (transferrequest length 8 kB—transfer unit 2 kB).

The transfer end judgment processing is carried out according to theflow shown in FIG. 23. First, the DMA controller 801 checks the residualtransfer length of the transfer register 804 (S5000). In this case, theresidual transfer length is equal to 6 kB, and thus the processing goesto “Yes”. It is checked whether the effective area length for theprocessor 1 in the script register 806 is equal to zero or not (S5001).As described above, the effective length for the processor 1 is equal tozero, and thus the processing goes to “No”. Then, the start scriptnumber for the processor 1 of the transfer start register 803 isincremented (S5002). Specifically, the start script number for theprocessor 1 is set to 1.

Subsequently, the DMA controller 801 checks the effective area lengthfor the processor 2 of the script register 806 (S5003). The effectivearea length for the processor 2 is equal to 2 kB as described above, andthus the processing goes to “Yes”.

The DMA controller 801 carries out the processing of S2000 again. Atthis time, the DMA controller 801 reads out the script indicated by thestart script number for the processor 1 in the transfer start register803 which is renewed in S5002. That is, the DMA controller 801 reads outthe script 1 for the processor 1 from the memory 1 (117) by executingthe processing from S3000 to S3001. Then, the DMA controller 801describes the #1 area head address described in the script 1 for theprocessor 1 into the transfer destination address column of the transferregister 804. The script identifier “1” described in the script 1 forthe processor 1 and “6 kB” described in the area length column aredescribed in the execution script number column for the processor 1 andthe effective area length column for the processor 1 in the scriptregister 806, respectively (S3002).

Subsequently, the DMA controller 801 determines the transfer unitaccording to the flow of FIG. 22 (S2001).

At this time point, the residual transfer length column of the transferregister 804 is equal to 6 kB (S4000).

Subsequently, the DMA controller 801 compares the effective area length6 kB of the processor 1 with the effective area length 2 kB of theprocessor 2 in the script register 806 (S4001). In this case, the formerlength is larger, and thus the processing goes to “No”. Then, theeffective area length 2 kB of the processor 2 is compared with theresidual transfer length 6 kB (S4005). In this case, the latter lengthis larger, and thus the processing goes to “Yes”. Accordingly, theeffective area length 2 kB of the processor 2 is determined as thetransfer unit (S4006).

The DMA controller 801 transfers the data stored at the transfer sourceaddress stored in the transfer register 804 to the transfer destinationaddress by only the data size of the transfer unit (S2002). That is, thedata of the memory 2 (113) is transferred to the cache memory 130 byonly 2 kB.

During execution of the transfer, the transfer source address, thetransfer destination address and the residual transfer length in thetransfer source address of the transfer register 804 are successivelyrenewed, and the effective area for the processor 2 and the effectivearea length for the processor 1 in the script register 806 aresuccessively reduced every data amount corresponding to the size of thetransferred data.

When the effective area length for the processor 2, the effective arealength for the processor 1 or the residual transfer length in the scriptregister 806 is equal to zero, the DMA controller 801 carries out thetransfer end judgment processing (S2003). At this time point, theeffective area length for the processor 2 of the script register 806 isequal to zero, the effective area length for the processor 1 is equal to4kB and the residual transfer length is equal to 4 kB (previous residualtransfer length 6 kB—transfer unit 2 kB).

The transfer end judgment processing is carried out according to theflow shown in FIG. 23. First, the DMA controller 801 checks the residualtransfer length of the transfer register 804 (S5000). In this case, theresidual transfer length is equal to 4 kB, and thus the processing goesto “Yes”. Then, it is checked whether the effective area length for theprocessor 1 of the script register 806 is equal to zero (S5001). Theeffective area length for the processor 1 is equal to 4 kB as describedabove, and thus the processing goes to “Yes”. Then, it is checkedwhether the effective area length for the processor 2 of the scriptregister 806 is equal to zero (S5003). The effective area for theprocessor 2 is equal to zero as described above, and thus the processinggoes to “No”, and the start script number for the processor 2 of thetransfer start register 803 is incremented (S5004). Specifically, thestart script number for the processor 2 is set to 1.

The DMA controller 801 executes the processing of S2000. At this time,the DMA controller 801 reads out the script indicated by the startscript number for the processor 2 of the transfer start register 803which is renewed in the S5004. That is, the DMA controller 801 reads outthe script 1 for the processor 2 from the memory 2 (117) by executingthe processing from S3000 to S3001. The DMA controller 801 sets the #1area head address described in the script 1 for the processor 2 into thetransfer source address column. The script identifier “1” described inthe script 1 for the processor 2 and “4 kB” described in the area lengthcolumn are described in the execution script number column for theprocessor 2 and the effective area length column for the processor 2 inthe script register 806, respectively (S3002).

Subsequently, the DMA controller 801 determines the transfer unitaccording to the flow of FIG. 22 again (S2001).

At this time point, “4 kB” is described in the residual transfer lengthcolumn of the transfer register 804 (S4000).

Subsequently, the DMA controller 801 compares the effective area length4 kB of the processor I with the effective area length 4 kB of theprocessor 2 in the script register 806 (S4001). In this case, the formerlength is equal to the latter length, and thus the processing goes to“No”. Then, the effective area length 4 kB of the processor 2 iscompared with the residual transfer length 4 kB (S4005). In this case,the former length is also equal to the latter length, and thus theprocessing goes to “No”. Accordingly, the residual transfer length 4 kBis determined as the transfer unit (S4007).

The DMA controller 801 transfers to the transfer destination address thedata stored in the transfer source address stored in the transferregister 804, the data amount of the data concerned corresponding toonly the data size of the transfer unit (S2002). That is, at this time,the data of the memory 2 (113) is transferred to the cache memory 130 byonly 4 kB.

During execution of the transfer, the transfer source address, thetransfer destination address and the residual transfer length in thetransfer register 804 are successively renewed, and also the effectivearea length for the processor 2 and the effective area length for theprocessor 1 in the script register 806 are successively reduced forevery amount corresponding to the size of the transferred data.

When the effective area length for the processor 2, the effective arealength for the processor or the residual transfer length in the scriptregister 806 is equal to zero, the DMA controller 801 carries out thetransfer end judgment processing (S2003). At this time point, all of theeffective area length for the processor 1 the effective area length forthe processor 2 and the residual transfer length are equal to zero.

The transfer end judgment processing is carried out according to theflow shown in FIG. 23. Since the residual transfer length is equal tozero, the processing goes to “No”, and the transfer processing isfinished. The DMA controller 801 writes into the memory 1 (117) the endstatus in which the result of the transfer processing is described(S1008), and transmits an end notification to the processor 1 (119)(S1009). The processor 1 (119) reads out the end status from the memory1 (117), and executes a processing corresponding to the content thereof(S1010). The processor 1 (119) transmits the end notification to theprocessor 2 (112) (S1011). The processor 2 (112) leaves open the storagearea of the memory 2 (113) in which the writing data is stored.

The data transfer processing is carried out as, described above when adata writing request of 8 kB is issued from the information processingdevice 200.

Second Embodiment

The first embodiment may be modified like the second embodiment shown inFIGS. 25 to 27. In the second embodiment, the data transfer is carriedout without using the script for the processor 2 in the firstembodiment.

In this case, the transfer data is stored in the memory 2 (113), but thescript for the processor 2 is not stored in the memory 1 (113) as shownin FIG. 25. In place of that, the area head address of the memory 2(113) is stored in the script for the processor 1 of the memory 1 (117)as shown in FIG. 26.

The processing flow of the data transfer carried out between the memory2 (113) and the cache memory 130 according to the second embodiment willbe described with reference to the flowchart of FIG. 27.

The processor 2 (112) secures the data area (S6000). The securement ofthe data area means that when the file access request transmitted fromthe information processing device 200 is a read-out request, a storagearea for storing the read-out data is secured in the memory 2 (113).When the file access request transmitted from the information processingdevice 200 is a reading request, the securement means that a storagearea for storing read-out data is secured in the memory 2 (113).

The processor 2 (112) transmits the data transfer request command (theinformation indicating the storage position of the data in the secondmemory) to the processor 1 (119) (S6001). The data transfer requestcommand contains the individual storage addresses of the data areasecured in S1000, the data size of each data, the request transferlength and the transfer direction.

Thereafter, the processor 1 (119) analyzes the data transfer requestcommand transmitted from the processor 2 (112) (S6002), there byrecognizing the data size of the storage address of the data in thememory 2 (112), the request transfer length and the transfer direction.

Subsequently, the processor 1 (119) secures the data area having thesize indicated by the request transfer length in the cache memory 130(S6003).

The processor 1 (119) creates the script for the processor 1 inconnection with each data area secured in the cache memory 130 (S6004),whereby the script for the processor 1 containing the informationindicating the storage position of the data in the cache memory 130 andthe information indicating the storage position of the data in thememory 2 (112) is written in the memory 1 (117).

Thereafter, the processor 1 (119) transmits the transfer startinformation containing the request transfer length, the transferdirection and the identifier of the script for the processor 1 to DMA114, and writes this data into the transfer start register 803 of DMA114, so that the processor 1 (119) starts the DMA 114 (S6005).

Accordingly, the DMA 114 starts the DMA transfer processing (S6006).

When the DMA transfer is finished, the DMA controller 801 writes intothe memory 1 (117) the end status in which the result of the transferprocessing is described (S6007), and it transmits an end notification tothe processor 1 (119) (S6008).

The processor 1 (119) reads out the end status from the memory 1 (117)and executes the processing corresponding to the content thereof(S6009). The processor 1 (119) transmits the end notification to theprocessor 2 (112) (S6010).

When the file access request is a data read-out request, the processor 2(112) may read out the read-out data transmitted to the data area of thememory 2 (113) and transmit the data to the information processingdevice 200. Furthermore, when the file access request is a data writingrequest, the processor 2 (112) leaves open the storage area of thememory 2 (113) in which the writing data are stored, so that the datacan be used in other processing.

As described, above, in the storage device controller 100 according tothis embodiment, the information on the storage position of the data inthe cache memory 130, etc. and the information on the storage positionof the data in the memory 2 (113), etc. are written into the memory 1(117) by the processor 1 (119). The DMA 114 reads out this informationfrom the memory 1 (117) to carry out the data transfer. Accordingly, theidle time of the processor 1 (119) can be reduced, and the processor 1(119) can be efficiently operated. Furthermore, the data reading/writingoperation carried out in response to the file access request from theinformation processing device 200 can be increased.

Furthermore, according to the storage device controlling device 100 ofthis embodiment, even when the data size of the transfer source and thedata size of the transfer destination are different from each other, thedata transfer is controlled by DMA 114 without carrying out control bythe processor 1 (119) and the processor 2 (112). Accordingly, theprocessing loads imposed on the processor 1 (119) and the processor 2(113) can be reduced, and the speed of the data reading/writingoperation carried out in response to the file access request from theinformation processing device 200 can be increased.

Furthermore, in the storage device controlling device 100 of thisembodiment, the end status is not written in the register of the DMA114, but is written in the memory 1 (117). The processor 1 (119) readsout the end status from the memory 1 (117), so that the reading time ofthe end status by the processor 1 (119) can be shortened. Therefore, theidle time of the processor 1 (119) can be reduced, whereby the speed ofthe data reading/writing operation carried out in response to the fileaccess request from the information processing device 200 also can beincreased.

In S1006, the transfer start information transmitted from the processor1 (119) to the DMA 114 is set not to contain the identifier of thescript for the processor 1. In this case, for example, the processor 1(112) is designed to store the identifier of the script for theprocessor 1 at a predetermined storage position in the memory 1 (117),and the DMA 114 is designed to read out the identifier of the script forthe processor 1 from the storage position concerned before the DMAtransfer processing in S6006 is started.

Third Embodiment

Furthermore, a third embodiment shown in FIG. 28 may be implemented.That is, in the third embodiment, the same DMA transfer as the firstembodiment or the second embodiment is implemented in the informationprocessing device 200, such as a computer or the like, which isconnected to a network, such as LAN 400 or the like.

The information processing device 200 is equipped with a processor 1(first processor) 209, a processor 2 (second processor) 202, DMA (datatransfer device) 204, a memory 1 (third memory) 207, a memory 2 (secondmemory) 203, a memory controller 1 (201), a memory controller 2 (201),an I/O controller 205 and a storage device (first memory) 210.

The processor 2 (202), the memory 2 (203) and the memory controller 2(201) provides a communication interface function for carrying outcommunications with other information processing devices 200 through LAN400. For example, the communication interface function will enablereception of a file access request transmitted from another informationprocessing device 200 through LAN 200 according to the TCP/IP protocoland effect control of the transmission/reception of data.

The processor 2 (202) carries out the overall control of the informationprocessing device 200 by executing various programs stored in the memory2 (203). Various programs and data are stored in the memory 2 (203). Forexample, data transmitted/received to/from the other informationprocessing devices 200 through LAN 400 are stored in the memory 2 (203).

The storage addresses (storage positions) of data stored in the memory 2(203) are managed by the processor 2 (202).

The processor 1 (209), the memory 1 (207), the DMA 204 and the memorycontroller 1 (201) transmit/receive data and commands to/from thestorage device 210 and the I/O controller 205. The processor 1 (209)makes DMA 114 execute transfer of the data stored in the memory 2 (203)to the storage device 210 and transfer of the data stored in the storagedevice 210 to the memory 2 (203). That is, the data transfer between thememory 2 (203) and the storage device 210 is carried out by the DMA 204.The processor 1 (209) makes the DMA 114 execute transfer of the datastored in the memory 2 (203) to the I/O controller 205 and transfer ofthe data stored in the I/O controller 205 to the memory 2 (203).Furthermore, the processor 1 (209) manages the storage addresses(storage positions) of the data stored in the storage device 210 and theI/O controllers 205, and the storage addresses (storage positions) ofthe data stored in the memory 1 (207).

The I/O controller 205 is connected to an input device 206 and an outputdevice 207, and it controls the transmission/reception of data betweeneach of the input device 206 and the output device 207 and theinformation processing device 200. The input device 206 is used to inputdata to the information processing device 200 by an operator operatingthe information processing device 200, etc. A keyboard, a mouse or thelike is used as the input device 206. The output device 207 is a devicefor outputting information to the external. A display, a printer or thelike is used as the output device 207. The storage device 210 may be ahard disk device, a semiconductor storage device or the like. As shownin FIG. 28, the storage device 210 may be equipped so as to be installedin the information processing device 200 or equipped at the external.

In the information processing device 200 of the third embodiment, thesame DMA transfer as the first embodiment or the second embodiment iscarried out between the memory 2 (203) and the storage device 210,between the memory 2 (203) and the I/O controller 205 or between the I/Ocontroller 205 and the storage device 210, whereby the idle time of theprocessor 1 (209) can be reduced and the processing efficiency can beenhanced. Accordingly, the speed of the data reading/writing from/intothe storage device 210 or the speed of the data input/output to/from theinput device 206/the output device 208 can be increased.

Various embodiments for implementing the present invention have beendescribed, and these embodiments are described in such a way as to makethe understanding of the present invention easy. Therefore, the presentinvention should not be interpreted as being limited to theseembodiments. That is, the above embodiments may be changed or improvedwithout departing from the subject matter of the present invention, andthe present invention may contain equivalents to the above-describedembodiments.

1. A storage system comprising: a storage controller for controlling thestorage system; and at least one disk device for storing data from saidstorage controller, wherein said storage controller comprises: a channelcontroller for receiving a file access input/output (I/O) request basedon file-name indication from an information processing device through anetwork, transmitting/receiving data to/from the information processingdevice and outputting a block access I/O request corresponding to thefile access I/O request, a disk controller for carrying out input/outputcontrol of data stored in a storage volume for storing the data based onthe block access I/O request output by said channel controller, a firstmemory including a cache memory for temporarily storing the datadelivered between the channel controller and the disk controller, and adata transfer network connected to said channel controller, said diskcontroller and said first memory, wherein the channel controller isequipped with a first processor for outputting the block access I/Orequest corresponding to the file access I/O request and controlling thefirst memory, a file access circuit which has a second processor and asecond memory controlled by the second processor and serves to controlthe transmission/reception of the file access I/O request and the datasent from/to the information processing device, a data transfer devicefor controlling data transfer between the first memory and the secondmemory, and a third memory controlled by the first processor, which areformed on a circuit module, and wherein the second processor transmitsinformation indicating the storage position of the data in the secondmemory to the first processor, the first processor writes into the thirdmemory data transfer information containing information indicating thestorage position of the data in the first memory and informationindicating the storage position of the data in the second memory, andthe data transfer device reads out the data transfer information fromthe third memory and controls the data transfer between the first memoryand the second memory based on the data transfer information thus readout.
 2. The storage system according to any one of claim 1, wherein thedata transfer device writes into the third memory information indicatingthe result of the data transfer carried out between the first memory andthe second memory.
 3. A storage system comprising: a storage controllerfor controlling the storage system; and at least one disk device forstoring data from said storage controller; wherein said storagecontroller comprises: a channel controller for receiving a file accessinput/output (I/O) request based on file-name indication from aninformation processing device through a network, transmitting/receivingdata to/from the information processing device and outputting a blockaccess 1/O request corresponding to the file access I/O request, a diskcontroller for carrying out input/output control of data stored in astorage volume for storing the data based on the block access I/Orequest output by said channel controller, a first memory including acache memory for temporarily storing the data delivered between thechannel controller and the disk controller, and a data transfer networkconnected to said channel controller, said disk controller and saidfirst memory, wherein the channel controller is equipped with a firstprocessor for outputting the block access I/O request corresponding tothe file access I/O request and controlling the first memory, a fileaccess circuit which has a second processor and a second memorycontrolled by the second processor and serves to control thetransmission/reception of the file access I/O request and the data whichis sent from/to the information processing device, a data transferdevice for controlling data transfer between the first memory and thesecond memory, and a third memory controlled by the first processor,which are formed on a circuit board, and wherein the second processortransmits information indicating the storage position of the data in thesecond memory to the first processor, the first processor writes intothe third memory data transfer information containing informationindicating the storage position of the data in the first memory andinformation indicating the storage position of the data in the secondmemory and transmits the storage position of the data transferinformation in the third memory to the data transfer device, and thedata transfer device reads out the data transfer information from thethird memory and controls the data transfer between the first memory andthe second memory based on the data transfer information thus read out.4. The storage system according to any one of claim 3, wherein the datatransfer device writes into the third memory information indicating theresult of the data transfer carried out between the first memory and thesecond memory.
 5. A storage system comprising: a storage controller forcontrolling the storage system; and at least one disk device for storingdata from said storage controller, wherein said storage controllercomprises: a channel controller for receiving a file access input/output(I/O) request based on file-name indication from an informationprocessing device through a network, transmitting/receiving data to/fromthe information processing device and outputting a block access I/Orequest corresponding to the file access I/O request, a disk controllerfor carrying out input/output control of data stored in a storage volumefor storing the data based on the block access I/O request output bysaid channel controller, a first memory including a cache memory fortemporarily storing the data delivered between the channel controllerand the disk controller, and a data transfer network connected to saidchannel controller, said disk controller and said first memory, whereinthe channel controller is equipped with a first processor for outputtingthe block access I/O request corresponding to the file access I/Orequest and controlling the first memory, a file access circuit whichhas a second processor and a second memory controlled by the secondprocessor and serves to control the transmission/reception of the fileaccess I/O request and the data sent from/to the information processingdevice, a data transfer device for controlling data transfer between thefirst memory and the, second memory, and a third memory controlled bythe first processor, which are formed on a circuit module, and whereinthe first processor writes into the third memory first data transferinformation containing information indicating the storage position ofthe data in the first memory, the second processor writes into thesecond memory second data transfer information containing informationindicating the storage position of the data in the second memory, andthe data transfer device reads out the second data transfer informationfrom the second memory, reads out the first data transfer informationfrom the third memory, and controls the data transfer between the firstmemory and the second memory based on the first data transferinformation and the second data transfer information.
 6. The storagesystem according to any one of claim 5, wherein the data transfer devicewrites into the third memory information indicating the result of thedata transfer carried out between the first memory and the secondmemory.
 7. A storage system comprising: a storage controller forcontrolling the storage system; and at least one disk device for storingdata from said storage controller, wherein said storage controllercomprises: a channel controller for receiving a file access input/output(I/O) request based on file-name indication from an informationprocessing device through a network, transmitting/receiving data to/fromthe information processing device and outputting a block access I/Orequest corresponding to the file access I/O request, a disk controllerfor carrying out input/output control of data stored in a storage volumefor storing the data based on the block access I/O request output bysaid channel controller, a first memory including a cache memory fortemporarily storing the data delivered between the channel controllerand the disk controller, and a data transfer network connected to saidchannel controller, said disk controller and said first memory, whereinthe channel controller is equipped with a first processor for outputtingthe block access I/O request corresponding to the file access I/Orequest and controlling the first memory, a file access circuit whichhas a second processor and a second memory controlled by the secondprocessor and serves to control the transmission/reception of the fileaccess I/O request and the data sent from/to the information processingdevice, a data transfer device for controlling data transfer between thefirst memory and the second memory, and a third memory controlled by thefirst processor, which are formed on a circuit module, and wherein thefirst processor writes into the third memory first data transferinformation containing information indicating the storage position ofthe data in the first memory, the second processor writes into thesecond memory second data transfer information containing informationindicating the storage position of the data in the second memory, thesecond processor transmits information indicating the storage positionof the second data transfer information to the first processor, thefirst processor transmits to the data transfer device transfer startinformation containing information indicating the storage position ofthe first data transfer information and information indicating thestorage position of the second data transfer information, and the datatransfer device reads out the second data transfer information from thesecond memory based on the transfer start information, reads out thefirst data transfer from the third memory on the basis of the transferstart information, and controls the data transfer between the firstmemory and the second memory based on the first data transferinformation and the second data transfer information.
 8. The storagesystem according to any one of claim 7, wherein the data transfer devicewrites into the third memory information indicating the result of thedata transfer carried out between the first memory and the secondmemory.
 9. A control method for a storage system including a storagecontroller for controlling the storage system; and at least one diskdevice for storing data from said storage controller, wherein saidstorage controller comprises: a channel controller for receiving a fileaccess input/output (I/O) request based on file-name indication from aninformation processing device through a network, transmitting/receivingdata to/from the information processing device and outputting a blockaccess I/O request corresponding to the file access I/O request, a diskcontroller for carrying out input/output control of data stored in astorage volume for storing the data based on the block access I/Orequest output by said channel controller, a first memory including acache memory for temporarily storing the data delivered between thechannel controller and the disk controller, and a data transfer networkconnected to said channel controller, said disk controller and saidfirst memory, the channel controller being equipped with a firstprocessor for outputting the block access I/O request corresponding tothe file access I/O request and controlling the first memory, a fileaccess circuit which has a second processor and a second memorycontrolled by the second processor and serves to control thetransmission/reception of the file access I/O request and the data sentfrom/to the information processing device, a data transfer device forcontrolling data transfer between the first memory and the secondmemory, and a third memory controlled by the first processor, which areformed on a circuit board, said control method comprising the steps of:transmitting, by the second processor, information indicating thestorage position of the data in the second memory to the firstprocessor; writing, by the first processor, into the third memory datatransfer information containing information indicating the storageposition of the data in the first memory and information indicating thestorage position of the data in the second memory; and by the datatransfer device, reading out the data transfer information from thethird memory, and controlling the data transfer between the first memoryand the second memory based on the data transfer information thus readout.
 10. The control method according to any one of claim 9, wherein thedata transfer device writes into the third memory information indicatingthe result of the data transfer carried out between the first memory andthe second memory.
 11. A control method for a storage system including astorage controller for controlling the storage system; and at least onedisk device for storing data from said storage controller, wherein saidstorage controller comprises: a channel controller for receiving a fileaccess input/output (I/O) request based on file-name indication from aninformation processing device through a network, transmitting/receivingdata to/from the information processing device and outputting a blockaccess I/O request corresponding to the file access I/O request, a diskcontroller for carrying out input/output control of data stored in astorage volume for storing the data based on the block access I/Orequest output by said channel controller, a first memory including acache memory for temporarily storing the data delivered between thechannel controller and the disk controller, and a data transfer networkconnected to said channel controller, said disk controller and saidfirst memory, the channel controller being equipped with a firstprocessor for outputting the block access I/O request corresponding tothe file access I/O request and controlling the first memory, a fileaccess circuit which has a second processor and a second memorycontrolled by the second processor and serves to control thetransmission/reception of the file access 1/O request and the data sentfrom/to the information processing device, a data transfer device forcontrolling data transfer between the first memory and the secondmemory, and a third memory controlled by the first processor, which areformed on a circuit module, said control method comprising the steps of:transmitting, by the second processor, information indicating thestorage position of the data in the second memory to the firstprocessor; by the first processor, writing into the third memory datatransfer information containing information indicating the storageposition of the data in the first memory and information indicating thestorage position of the data in the second memory, and transmitting thestorage position of the data transfer information in the third memory tothe data transfer device; and by the data transfer device reading outthe data transfer information from the third memory, and controlling thedata transfer between the first memory and the second memory based onthe data transfer information thus read out.
 12. The control methodaccording to any one of claim 11, wherein the data transfer devicewrites into the third memory information indicating the result of thedata transfer carried out between the first memory and the secondmemory.
 13. A control method for a storage system including a storagecontroller for controlling the storage system; and at least one diskdevice for storing data from said storage controller, wherein saidstorage controller comprises: a channel controller for receiving a fileaccess input/output (I/O) request based on file-name indication from aninformation processing device through a network, transmitting/receivingdata to/from the information processing device and outputting a blockaccess I/O request corresponding to the file access I/O request, a diskcontroller for carrying out input/output control of data stored in astorage volume for storing the data based on the block access I/Orequest output by said channel controller, a first memory including acache memory for temporarily storing the data delivered between, thechannel controller and the disk controller, and a data transfer networkconnected to said channel controller, said disk controller and saidfirst memory, the channel controller being equipped with a firstprocessor for outputting the block access I/O request corresponding tothe file access I/O request and controlling the first memory, a fileaccess circuit which has a second processor and a second memorycontrolled by the second processor and serves to control thetransmission/reception of the file access I/O request and the data whichis sent from/to the information processing device, a data transferdevice for controlling data transfer between the first memory and thesecond memory, and a third memory controlled by the first processor,which are formed on a circuit board, said control method comprising thesteps of: writing, by the first processor into the third memory firstdata transfer information containing information indicating the storageposition of the data in the first memory; writing, by the secondprocessor, into the second memory second data transfer informationcontaining information indicating the, storage position of the data inthe second memory; and by the data transfer device, reading out thesecond data transfer information from the second memory, reading out thefirst data transfer information from the third memory, and controllingthe data transfer between the first memory and the second memory basedon the first data transfer information and the second data transferinformation.
 14. The control method according to any one of claim 13,wherein the data transfer device writes into the third memoryinformation indicating the result of the data transfer carried outbetween the first memory and the second memory.
 15. A control method fora storage system including a storage controller for controlling thestorage system; and at least one disk device for storing data from saidstorage controller, wherein said storage controller comprises: a channelcontroller for receiving a file access input/output (I/O) request basedon file-name indication from an information processing device through anetwork, transmitting/receiving data to/from the information processingdevice and outputting a block access I/O request corresponding to thefile input/output request, a disk controller for carrying outinput/output control of data stored in a storage volume for storing thedata based on the block access I/O request output by said channelcontroller, a first memory including a cache memory for temporarilystoring the data delivered between the channel controller and the diskcontroller, and a data transfer network connected to said channelcontroller, said disk controller and said first memory, the channelcontroller being equipped with a first processor for outputting theblock access I/O request corresponding to the file access I/O requestand controlling the first memory, a file access circuit which has asecond processor and a second memory controlled by the second processorand serves to control the transmission/reception of the file access I/Orequest and the data which is sent from/to the information processingdevice, a data transfer device for controlling data transfer between thefirst memory and the second memory, and a third memory controlled by thefirst processor, which are formed on a circuit module, said controlmethod comprising the steps of: writing, by the first processor, intothe third memory first data transfer information containing informationindicating the storage position of the data in the first memory;writing, by the second processor, into the second memory second datatransfer information containing information indicating the storageposition of the data in the second memory; transmitting, by the secondprocessor, information indicating the storage position of the seconddata transfer information to the first processor; transmitting, by thefirst processor, to the data transfer device transfer start informationcontaining information indicating the storage position of the first datatransfer information and information indicating the storage position ofthe second data transfer information; and by the data transfer device,reading out the second data transfer information from the second memorybased on the transfer start information, reading out the first datatransfer from the third memory, based on the transfer start information,and controlling the data transfer between the first memory and thesecond memory based on the first data transfer information and thesecond data transfer information.
 16. The control method according toany one of claim 15, wherein the data transfer device writes into thethird memory information indicating the result of the data transfercarried out between the first memory and the second memory.